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M48T251Y M48T251V
5.0 or 3.3V, 4096K TIMEKEEPER(R) SRAM with PHANTOM
FEATURES SUMMARY s 5.0V OR 3.3V OPERATING VOLTAGE
s
Figure 1. 32-pin, DIP Package
REAL TIME CLOCK KEEPS TRACK OF TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAYS, DATE OF THE MONTH, MONTHS, and YEARS AUTOMATIC LEAP YEAR CORRECTION VALID UP TO THE YEAR 2100 AUTOMATIC SWITCH-OVER and DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT VOLTAGES: (VPFD = Power-fail Deselect Voltage): - M48T251Y: 4.25V VPFD 4.50V - M48T251V: 2.80V
s
s
32 1
s
PMDIP32 (PM)
VPFD 2.97V
s s
FULL 10% VCC OPERATING RANGE OVER 10 YEARS' DATA RETENTION IN THE ABSENCE OF POWER WATCH FUNCTION IS TRANSPARENT TO RAM OPERATION 512K x 8 NV SRAM DIRECTLY REPLACES VOLATILE STATIC RAM OR EEPROM
s
s
March 2003
Rev. 2.0
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M48T251Y, M48T251V
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....4 .....4 .....4 .....5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Memory READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Memory WRITE Cycle 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. Memory WRITE Cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Memory AC Characteristics, M48T251Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Memory AC Characteristics, M48T251V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PHANTOM CLOCK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. Comparison Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Oscillator and Reset Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Zero Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 10. Phantom Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. Phantom Clock READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. Phantom Clock WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13. Phantom Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. Phantom Clock AC Characteristics (M48T251Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 12. Phantom Clock AC Characteristics (M48T251V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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SUMMARY DESCRIPTION The M48T251Y/V TIMEKEEPER(R) RAM is a 512Kbit x 8 non-volatile static RAM and real time clock organized as 524,288 words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock solution. In the event of power instability or absence, a self-contained battery maintains the timekeeping operation and provides power for a CMOS static RAM. Control circuitry monitors VCC and invokes write protection to prevent data corruption in the memory and RTC. The clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, day, date, month,
and year information. The last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. The clock operates in one of two formats: - a 12-hour mode with an AM/PM indicator; or - a 24-hour mode The M48T251Y/V is a 32-pin (PM) DIP module that integrates the RTC, the battery, and SRAM in one package. The modules are shipped in plastic, anti-static tubes (see Table 14, page 22).
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A18 RST CE Address Input Reset Input Chip Enable Output Enable Input WRITE Enable Input Data Inputs/Outputs Supply Voltage Input Ground
A0-A18 WE CE OE RST M48T251Y M48T251V
DQ0-D7
OE WE DQ0-DQ7 VCC VSS
Figure 3. DIP Connections
VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
AI04239
VSS
AI04237
A18/RST A16 A14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
M48T251Y M48T251V
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A12
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
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M48T251Y, M48T251V
Figure 4. Block Diagram
XO 32.768 Hz CRYSTAL XI UPDATE READ CE OE WE RST SRAM CONTROL LOGIC WRITE POWER FAIL A0-A16 DQ0-DQ7 TIMEKEEPER REGISTER CLOCK/CALENDAR LOGIC
ACCESS ENABLE SEQUENCE DETECTOR
COMPARISON REGISTER
DQ0
I/O BUFFERS
DATA
INTERNAL VCC
VCC
POWER-FAIL DETECT LOGIC
VBAT
AI04238
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MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TA TSTG TSLD(1) VCC VIO IO PD Parameter Operating Temperature Storage Temperature (VCC, Oscillator Off) Lead Solder Temperature for 10 seconds Supply Voltage (on any pin relative to Ground) Input or Output Voltages Output Current Power Dissipation M48T251Y M48T251V Value 0 to 70 -40 to 85 260 -0.3 to +7.0 -0.3 to +4.6 -0.3 to VCC + 0.3 20 1 Unit C C C V V V mA W
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION! Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up Mode.
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M48T251Y, M48T251V
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 3. DC and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M48T251Y 4.5 to 5.5V 0 to 70C 100pF 5ns 0 to 3V 1.5V M48T251V 3.0 to 3.6V 0 to 70C 50pF 5ns 0 to 3V 1.5V
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Note: Output High Z is defined as the point where data is no longer driven (see Table 3, page 7).
Figure 5. AC Testing Load Circuit
VCCI
1.1 K DEVICE UNDER TEST 680
CL = 50 pF
AI04240
Note: 50pF for M48T251V.
Table 4. Capacitance
Symbol CIN CIO(3) Parameter(1,2) Input Capacitance Input / Output Capacitance Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only; not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs were deselected.
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Table 5. DC Characteristics
M48T251Y Sym Parameter(1) Test Condition Min ILI(2) ILO ICC1 ICC2 ICC3 VIL(3) VIH(3) VOL VOH Input Leakage Current Output Leakage Current Supply Current Supply Current (TTL Standby) VCC Power Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.0 mA IOH = -1.0 mA 2.4 4.25 4.37 VBAT 4.50 CE = VIH CE = VCCI - 0.2 -0.3 2.2 5 3 0V VIN VCC 0V VOUT VCC -70 Typ Max 1 1 85 10 5 0.8 VCC + 0.3 0.4 2.4 2.80 2.5 2.97 -0.3 2.2 5 2 Min M48T251V -85 Typ Max 1 1 50 7 3 0.6 VCC + 0.3 0.4 A A mA mA mA V V V V V V Unit
VPFD(3) Power Fail Deselect VSO(3) Battery Back-up Switchover
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. RST (Pin 1) has an internal pull-up resistor. 3. All voltages are referenced to Ground.
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OPERATION MODES Table 6. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min)(1) VSO(1) 4.5V to 5.5V or 3.0V to 3.6V VCC CE VIH VIL VIL VIL X X OE X X VIL VIH X X WE X VIL VIH VIH X X DQ7-DQ0 High-Z DIN DOUT High-Z High-Z High-Z Power Standby Active Active Active CMOS Standby Battery Back-Up
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage 1. See Table 9, page 14 for details.
READ A READ cycle executes whenever WRITE Enable (WE) is high and Chip Enable (CE) is low (see Figure 6). The distinct address defined by the 19 address inputs (A0-A18) specifies which of the 512K bytes of data is to be accessed. Valid data will be accessed by the eight data output drivers within the specified Access Time (tACC) after the last address input signal is stable, the CE and OE access times, and their respective parameters are satisfied. When CE tACC and OE tACC are not satisfied, then data access times must be measured from the more recent CE and OE signals, with the limiting parameter being tCO (for CE) or tOE (for OE) instead of address access. Figure 6. Memory READ Cycle
tRC ADDRESSES tACC tCO CE
WRITE WRITE Mode (see Figure 7, page 10 and Figure 8, page 11) occurs whenever CE and WE signals are low (after address inputs are stable). The most recent falling edge of CE and WE will determine when the WRITE cycle begins (the earlier, rising edge of CE or WE determines cycle termination). All address inputs must be kept stable throughout the WRITE cycle. WE must be high (inactive) for a minimum recovery time (tWR) before a subsequent cycle is initiated. The OE control signal should be kept high (inactive) during the WRITE cycles to avoid bus contention. If CE and OE are low (active), WE will disable the outputs for Output Data WRITE Time (tODW) from its falling edge.
tOH
tOD tOE OE
tCOE
tCOE DQ0 - DQ7
DATA OUTPUT VALID
tODO
AI04230
Note: WE is high for a READ cycle.
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M48T251Y, M48T251V
Figure 7. Memory WRITE Cycle 1
tWC ADDRESSES tAW
CE tWR tWP WE tOEW tODW
HIGH IMPEDANCE
DQ0-DQ7
tDS
DATA IN STABLE
tDH
AI04231
Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If the CE low transition occurs simultaneously with or later than the WE low transition in WRITE Cycle 1, the output buffers remain in a high impedance state during this period. 3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period.
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Figure 8. Memory WRITE Cycle 2
WE = VIH ADDRESSES
VIH VIL
tWC
VIH VIL VIH VIL
tAW tWP CE
VIH VIL VIL VIH
tWR
tOEW
WE
VIL
VIL
tODW tCOE
DQ0-DQ7
tDS
VIH VIL DATA IN STABLE
tDH
VIH VIL
AI04232
Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period.
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M48T251Y, M48T251V
Table 7. Memory AC Characteristics, M48T251Y
Symbol tAVAV tAVQV tELQV tGLQV tELQX tGLQX tAXQX tEHQZ tGHQZ tWLQZ tAVAV tWLWH tELEH tAVEL tAVWL tEHAX tWHAX tWHQX tDVEH tDVWH tWHDX tEHDX
Note: 1. 2. 3.
Parameter(1) READ Cycle Time Access Time Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable or Output Enable Low to Output Transition Output Hold from Address Change Chip Enable or Output Enable High to Output Hi-Z Output Hi-Z from WE WRITE Cycle Time WE, CE Pulse Width Address Setup Time WRITE Recovery Time Address Hold Time from WE Output Active from WE Data Setup Time Data Hold Time from WE Data Hold Time from CE
M48T251Y-70 Unit Min 70 70 70 35 5 5 25 25 70 50 0 15 0 5 30 0 10 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRC tACC tCO tOE tCOE
tOH
tOD(2) tODW(2) tWC tWP(3) tAW tWR1 tWR2 tOEW tDS(4) tDH1(4) tDH2(4)
Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). These parameters are sampled with a 5 pF load are not 100% tested. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH and tDS are measured from the earlier of CE or WE going high.
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Table 8. Memory AC Characteristics, M48T251V
Symbol tAVAV tAVQV tELQV tGLQV tELQX tGLQX tAXQX tEHQZ tGHQZ tWLQZ tAVAV tWLWH tELEH tAVEL tAVWL tEHAX tWHAX tWHQX tDVEH tDVWH tWHDX tEHDX tRC tACC tCO tOE tCOE tOH tOD(2) tODW(2) tWC tWP1(3) tWP2 tAW tWR1(4) tWR2 tOEW tDS(5) tDH1(5) tDH2 READ Cycle Time Access Time Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable or Output Enable Low to Output Transition Output Hold from Address Change Chip Enable or Output Enable High to Output Hi-Z Output Hi-Z from WE WRITE Cycle Time WRITE Enable Pulse Width Chip Enable Pulse Width Address Setup Time WRITE Recovery Time Address Hold Time from WE Output Active from WE Data Setup Time Data Hold Time from WE Data Hold Time from CE 85 65 75 0 15 5 5 35 0 15 5 5 35 30 Parameter(1) M48T251V-85 Unit Min 85 85 85 45 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 5. tDH and tDS are measured from the earlier of CE or WE going high.
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Data Retention Mode Data can be read or written only when VCC is greater than VPFD. When VCC is below VPFD (the point at which write protection occurs), the clock registers and the SRAM are blocked from any access. When VCC falls below the Battery Switch Over threshold (VSO), the device is switched from VCC to battery backup (VBAT). RTC operation and SRAM data are maintained via battery backup until power is stable. All control, data, and address signals must be powered down when VCC is powered down. The lithium power source is designed to provide power for RTC activity as well as RTC and RAM Figure 9. Power Down/Up Mode AC Waveforms
VCC tF VPFD (max) tR
data retention when VCC is absent or unstable. The capability of this source is sufficient to power the device continuously for the life of the equipment into which it has been installed. For specification purposes, life expectancy is ten (10) years at 25C with the internal oscillator running without VCC. Each unit is shipped with its energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPFD, the energy source is enabled for battery backup operation. The actual life expectancy will be much longer if no battery energy is used (e.g., when VCC is present).
VPFD (min)
VSO
tFB
tPD
tREC
CE tDR
AI04236
Table 9. Power Down/Up Trip Points DC Characteristics
Symbol tREC tF tFB tR tPD tDR(2) Parameter(1) VPFD (max) to CE low VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time CE High to Power-Fail Expected Data Retention Time Min 1.5 300 10 0 0 10 Max 2.5 Unit ms
s s s s
Years
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. At 25C, VCC = 0V; the expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running.
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M48T251Y, M48T251V
PHANTOM CLOCK OPERATION Communication with the Phantom Clock is established by pattern recognition of a serial bit-stream of 64 bits which must be matched by executing 64 consecutive WRITE cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 READ or WRITE cycles either extract or update data in the clock while disabling the memory. Data transfer to and from the timekeeping function is accomplished with a serial bit-stream under control of Chip Enable (CE), Output Enable (OE), and WRITE Enable (WE). Initially, a READ cycle using the CE and OE control of the clock starts the pattern recognition sequence by moving the pointer to the first bit of the 64-bit comparison register (see Figure 10, page 16). Next, 64 consecutive WRITE cycles are executed using the CE and WE control of the device. These 64 WRITE cycles are used only to gain access to the clock. Therefore, any address to the memory is acceptable. However, the WRITE cycles generated to gain access to the Phantom Clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set
aside just one address location in RAM as a Phantom Clock scratch pad. When the first WRITE cycle is executed, it is compared to Bit 1 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next WRITE cycle. If a match is not found, the pointer does not advance and all subsequent WRITE cycles are ignored. If a READ cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 WRITE cycles as described above until all of the bits in the comparison register have been matched. With a correct match for 64-bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock.
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M48T251Y, M48T251V
Figure 10. Comparison Register Definition
Hex Value C5
7 BYTE 0 1
6 1
5 0
4 0
3 0
2 1
1 0
0 1
BYTE 1
0
0
1
1
1
0
1
0
3A
BYTE 2
1
0
1
0
0
0
1
1
A3
BYTE 3
0
1
0
1
1
1
0
0
5C
BYTE 4
1
1
0
0
0
1
0
1
C5
BYTE 5
0
0
1
1
1
0
1
0
3A
BYTE 6
1
0
1
0
0
0
1
1
A3
BYTE 7
0
1
0
1
1
1
0
0
5C
AI04262
Note: The odds of this pattern being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 1019. This pattern is sent to the clock LSB to MSB.
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M48T251Y, M48T251V
Clock Register Information Clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one (1) bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the clock registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These READ/WRITE registers are defined in the clock register map (see Table 10). Data contained in the clock registers is in Binary Coded Decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all eight registers, starting with Bit 0 of Register 0 and ending with Bit 7 of Register 7. Clock Accuracy The RTC is guaranteed to keep time accuracy to with 1 minute per month at 25C. The clock is factory-tuned with special calibration elements, and does not require additional calibration. Moderate temperature deviation will have a negligible effect in most applications. AM-PM/12/24 Mode Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When it is high, the 12hour mode is selected. In the 12-hour mode, Bit 5 is the AM/PM bit with the logic high being "PM." In the 24-hour mode, Bit 5 is the second 10-hour bit (20-23 hours). Oscillator and Reset Bits Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin input. When the reset bit is set to logic '1,' the Reset Input pin is ignored. When the reset bit logic is set to '0,' a low input on the reset pin will cause the device to abort data transfer without changing data in the timekeeping registers. Reset operates independently of all other inputs. Bit 5 controls the oscillator. When set to logic '0,' the oscillator turns on and the RTC/calendar begins to increment. Zero Bits Registers 1, 2, 3, 4, 5, and 6 contain one (1) or more bits that will always read logic '0.' When writing to these locations, either a logic '1' or '0' is acceptable.
Table 10. Phantom Clock Register Map
Register 0 1 2 3 4 5 6 7 0 0 12/24 0 0 0 0 0 0 0 10 Years 0 D7 D6 D5 D4 D3 D2 D1 D0 Function/Range BCD Format Seconds Seconds Minutes Hours Day Date Month Year 00-99 00-59 00-59 01-12/ 00-23 01-7 01-31 01-12 00-99
0.1 Seconds 10 Seconds 10 Minutes 10 / A/P OSC Hrs RST 0
0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of the Week Date: Day of the Month Month Year
RST = Reset Bit 0 = Must be set to '0'
10 date 10M
Keys: A/P = AM/PM Bit 12/24 = 12 or 24-hour mode Bit OSC = Oscillator Bit
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M48T251Y, M48T251V
Figure 11. Phantom Clock READ Cycle
WE tRC tCW tCO CE tOW tOD tRR
OE tOE tOEE tCOE Q DATA OUTPUT VALID
AI04259
tODO
Figure 12. Phantom Clock WRITE Cycle
OE tWC tWP tWR
WE tCW CE t DH tDS D DATA INPUT STABLE
AI04261
tWR
tDH
Figure 13. Phantom Clock Reset
tRST RST
AI04235
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M48T251Y, M48T251V
Table 11. Phantom Clock AC Characteristics (M48T251Y)
Symbol tAVAV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tRC tCO tOE tCOE tOEE tOD(2) tODO(2) tRR tAVAV tWLWH tEHAX tDVEH tWHDX tEHDX tELEH tWC tWP(3) tWR(4) tDS(5) tDH1(5) tDH2(5) tCW tRST Parameter(1) READ Cycle Time CE Access Time OE Access Time CE to Output Low Z OE to Output Low Z CE to Output High Z OE to Output High Z READ Recovery WRITE Cycle Time WRITE Pulse Width WRITE Recovery Data Setup Time Data Hold Time from WE Data Hold Time from CE CE Pulse Width RST Pulse Width 10 65 55 10 30 0 0 55 65 5 5 25 25 Min 65 55 55 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load and are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 5. tDH and tDS are measured from the earlier of CE or WE going high.
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M48T251Y, M48T251V
Table 12. Phantom Clock AC Characteristics (M48T251V)
Symbol tAVAV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tRC tCO tOE tCOE tOEE tOD(2) tODO(2) tRR tAVAV tWLWH tEHAX tDVEH tWHDX tEHDX tELEH tWC tWP(3) tWR(4) tDS(5) tDH1(5) tDH2(5) tCW tRST Parameter(1) READ Cycle Time CE Access Time OE Access Time CE to Output Low Z OE to Output Low Z CE to Output High Z OE to Output High Z READ Recovery WRITE Cycle Time WRITE Pulse Width WRITE Recovery Data Setup Time Data Hold Time from WE Data Hold Time from CE CE Pulse Width RST Pulse Width 20 85 60 20 35 0 0 65 85 5 5 30 30 Min 85 85 85 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load and are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 5. tDH and tDS are measured from the earlier of CE or WE going high.
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M48T251Y, M48T251V
PACKAGE MECHANICAL INFORMATION Figure 14. PMDIP32 - 32-pin Plastic Module DIP, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Note: Drawing is not to scale.
Table 13. PMDIP32 - 32-pin Plastic Module DIP, Package Mechanical Data
mm Symb Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 34.29 14.99 3.05 1.91 32 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 41.91 16.00 3.81 2.79 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.350 0.590 0.120 0.075 32 Max 0.375 - 0.023 0.013 1.700 0.740 0.110 1.650 0.630 0.150 0.110 inches
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M48T251Y, M48T251V
PART NUMBERING Table 14. Ordering Information Example
Example: M48T 251Y -70 PM 1 TR
Device Type M48T
Supply Voltage and Write Protect Voltage 251Y = VCC = 4.5 to 5.5V; VPFD = 4.25 to 4.50V 251V = VCC = 3.0 to 3.6V; VPFD = 2.80 to 2.97V
Speed -70 = 70ns (M48T251Y) -85 = 85ns (M48T251V)
Package PM = PMDIP32
Temperature Range 1 = 0 to 70C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M48T251Y, M48T251V
REVISION HISTORY Table 15. Document Revision History
Date June 2001 20-May-02 28-Mar-03 Rev. # 1.0 1.1 2.0 First Issue Add countries to disclaimer v2.2 template applied; test condition updated (Table 9) Revision Details
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M48T251Y, M48T251V
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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